http://www.semiconductor.net/article/CA6498840.html Semiconductor Internation 11/8/2007 Tokyo Electron Ltd. (TEL, Tokyo) formally joined Sematech's 3-D Interconnect Program, the first semiconductor supplier to officially team up with the Sematech member devicemakers, which are the program's founding members. http://www.semiconductor.net/articleXML/LN682223691.html?industryid=47304&nid=3574 Business Wire 10/9/2007 Nextreme has integrated cooling and power generation into the widely accepted copper pillar bumping process used in high-volume electronic packaging. This breakthrough addresses two of the most serious issues in electronics today - thermal and power management constraints. http://www.semiconductor.net/articleXML/LN684008289.html?industryid=47304&nid=3574 US Fed News 10/12/2007 Ming Fang and Valery Dubin, both of Portland, Ore., and Daoqiang Lu of Chandler, Ariz., have developed large bumps. According to the U.S. Patent & Trademark Office: "The invention provides bumps between a die and a substrate with a height greater than or equal to a height of a waveguide between the die and the substrate. The bumps may be formed on a die prior to that die being singulated from a wafer." http://www.semiconductor.net/articleXML/LN682868844.html?industryid=47304&nid=3574 Business Wire 10/10/2007 According to a recently published BCC Research report,THE GLOBAL MARKET FOR ADVANCED ELECTRONIC PACKAGING (SMC066A),the total market for semiconductor packaging and testing services will grow from $39.5 billion in 2006 to $57.6 billion in 2011 at a CAGR of 7.8%. http://www.semiconductor.net/article/CA6482835.html?industryid=47304&nid=3574 Semiconductor International 10/1/2007 Where do you draw the line of distinction between wafer-level packaging (WLP) and 3-D integration? Ask a handful of people, and you're likely to get some very different answers. http://www.semiconductor.net/article/CA6492524.html Semiconductor International 10/18/2007 "Ten years from now we won't be asking 'Why 3-D?,' we'll be asking 'Why 2-D?'" said Jochen Reisinger of Infineon Technologies AG (Munich, Germany). Reisinger was one of four panelists who discussed 3-D integration for system design at IMEC's annual review meeting, held Oct. 15-16. http://www.semiconductor.net/article/CA6501033.html?industryid=47304&nid=3572 Semiconductor International, 11/14/2007 Thermal considerations, stacking and connecting electronics to the outside world continue to be major packaging concerns. Although major technical hurdles arising from the endemic shrinking of architectures and system-in-a-chip (SiC) configurations continually raise the bar, research progresses to balance the technology equation. At the 40th International IMAPS symposium being held in San Jose this week, successful results of advanced work in the packaging field are being reported by those investigating options. http://smt.pennnet.com/display_article/311903/35/ARTCL/none/none/1/Infineon,-ASE-Produce-Embedded-Wafer-level-BGA/?pc=ENL SMT, November 13, 2007 NEUBIBERG, Germany and KAOHSIUNG, Taiwan - Infineon Technologies and packaging house Advanced Semiconductor Engineering Inc. (ASE) partnered to introduce BGA packages with a higher integration level, providing a reportedly near-infinite number of contact elements. Embedded wafer-level ball grid array (eWLB) packaging is said to offer 30% smaller form factors than lead-frame laminate devices. http://www.imaps.org/membership/corpbulletin/archives/2007/2007dec14.htm#aim IMAPS Bulletin December 14th 2007 AIM is pleased to announce the development of One-Step Underfill 688, a non-odorous, low surface tension, reworkable one component epoxy resin designed as a one-step underfill for flip chip, CSP, BGA and µBGA assemblies. http://www.imaps.org/membership/corpbulletin/archives/2007/2007dec14.htm#evgroup IMAPS Bulletin December 14th 2007 A key industry milestone has been reached surrounding the handling and processing of ultrathin wafers. In their ongoing joint development work, EV Group (EVG), a leading supplier of wafer-bonding and lithography equipment for the advanced semiconductor and packaging, MEMS, silicon-on-insulator (SOI) and emerging nanotechnology markets, and Brewer Science, Inc., the pioneer of industry-enabling technologies solutions for the semiconductor/microelectronics chemicals and equipment marketplace, unveiled they have demonstrated temporary wafer bonding capabilities for a wide range of backside processes, including through-silicon vias (TSVs) and backside metallization. http://www.imaps.org/membership/corpbulletin/archives/2007/2007dec14.htm#asymtek IMAPS Bulletin December 14th 2007 Asymtek, a Nordson company has announced that it has received the 2007 Global Technology Award in the Dispensing Equipment category for its SC-400 PreciseCoatT Conformal Coating Jet. The award recognizes the best new innovations in the printed circuit assembly and packaging industries. Sponsored by Global SMT & Packaging magazine, the award was presented at the Productronica trade show in Munich, Germany on Tuesday, November 13th, 2007. This was the third consecutive year Asymtek has won the award. http://www.edn.com/article/CA6512742.html?nid=3351&rid=418746834 Electronic News, 12/13/2007 To further the transformation of ON Semiconductor Corp. into an analog and power semiconductor giant with what the company says is enhanced scale, higher value and higher margin products, deep customer relationships and an expanded addressable market, the Phoenix, Ariz.-based power semiconductor supplier announced today it is acquiring AMIS Holdings Inc., the parent company of AMI Semiconductor (AMIS) in an all-stock transaction valued at approximately $915 million. http://www.semiconductor.net/article/CA6505618.html?industryid=47304&nid=357 Semiconductor International, 12/1/2007 A novel approach targeted at resolving some of the electronics industry's biggest thermal and power management challenges in high-end flip-chipped devices is, not surprisingly, attracting lots of attention. Nextreme Inc. (Research Triangle Park, N.C.) has developed thermally active copper pillar bumps that, when an electrical current is passed through, are capable of rapidly cooling one side relative to the other. Just reverse the process and pass heat through the thermal bump to generate power. And there's no limit to how small the geometry of the bump can go - it can scale right along with the bumping process and the chip side. http://www.trafalgar2.com/regions/uk/index.php?option=com_content&task=view&id=2244&Itemid=115 Global SMT & Packaging Tuesday, 18 December 2007 As consumers continue to push electronics manufacturers for smaller yet higher functioning products, packaging engineers must keep pace with the development of devices that can meet these demands. Newer generation stacked die CSP (SCSP) and emerging stacked package - or package on package (POP) - technologies are addressing the miniaturization challenge, but certainly not without some obstacles of their own. http://www.semiconductor.net/article/CA6517692.html?nid=3351&rid=418746834 Semiconductor International, 1/7/2008 Intel Corp. (Santa Clara) will introduce die stacking in products targeting the graphics market, predicts market research firm In-Stat (Scottsdale, Ariz.) in a new report that analyzes Intel's new product lineup and product strategies. The report studies Intel's expansion into new market segments, including discrete graphics, consumer electronics, and ultra mobile devices (UMDs). http://www.semiconductor.net/articleXML/LN725137436.html?industryid=47304&nid=3572 Business Wire, January 7, 2008 Monday Tessera's SHELLCASE(R) RT Wafer-Level Chip-Scale Packaging (WLCSP) technology is now available for packaging 300mm (12") wafers. The SHELLCASE RT solution is a high-yield, highly reliable manufacturing solution for image sensors used in next-generation mobile devices including mobile phones and PDAs. The technology enables very low profile camera modules, providing OEMs with greater design flexibility and an innovative tool in the development of thinner mobile devices. http://www.semiconductor.net/article/CA6518415.html?nid=3572 Semiconductor International, 1/9/2008 Nextreme Thermal Solutions (Durham, N.C.) announced a version of its thin-film thermal bump technology optimized for cooling hot spots in laser diodes, LEDs and sensors. Unlike conventional solder bumps, Nextreme's bumps function as microscale solid-state heat pumps. The new thermoelectric module - called the Ultra-High Packing Fraction (UPF) OptoCooler module - is designed to control temperatures in optoelectronics, electronics, medical, military and aerospace applications. http://www.semiconductor.net/article/CA6528422.html?nid=3572 Semiconductor International, 2/4/2008 Responding to the industry's call for new advanced packaging and interconnect materials to support emerging flip-chip and optical interconnect technologies, Rensselaer Polytechnic Institute (RPI, Troy, N.Y.) researchers teamed up with Polyset Co. (Mechanicville, N.Y.) to develop a polymer that should help solve redistribution layer challenges and ease future transitions from conventional lithography processes to next-generation on-chip nanoimprinting.